Much of today's high-density integrated circuitry has been made possible by small-geometry CMOS (Complementary Metal Oxide Semiconductor) technology, well known to those skilled in the art of semiconductor processing. Most modern microprocessors and large-scale integrated circuits are made using small-geometry CMOS processes (2 micron line widths and below).
CMOS technology is particularly desirable in military and aerospace applications because of its high noise immunity and low power consumption. However, military and aerospace environments tend to be characterized by high levels of radiation, particularly electron and proton radiation, and standard CMOS circuits are known to have some problems with high-radiation environments. While it is possible to construct radiation shields for CMOS military applications, this tends to add weight, expense, and complexity; requires extensive testing; and negates much of the desirability of CMOS for these applications.
"Radiation hardness" refers to the ability of a semiconductor device to withstand radiation without alteration of its electrical characteristics. A semiconductor device is said to be radiation hardened (rad-hard), radiation tolerant, or radiation resistant if it can continue to function within specifications after exposure to a specified amount of radiation. Semiconductor devices can be damaged or destroyed by the effects of nuclear radiation from natural and man-made sources. Radiation changes the electrical properties of solid state devices, leading to possible failure of any system incorporating them.
Ionization is the principal agent that damages or destroys CMOS devices. It is caused by photon (gamma or X ray) interactions, fast neutron interactions, and charged (alpha and beta) particles.
As the dose of ionizing radiation increases, the number of carriers generated in silicon will increase. Out in space it might take many years for a device to absorb high levels of radiation. For example, it might take 20 years for an IC (integrated circuit) to absorb a total dose of 100,000 rads(Si). However, in the presence of a nuclear explosion, a device might reach this total dose within hundreds of nanoseconds. This type of pulse photon exposure is referred to as (extreme) transient radiation.
Particularly troublesome to CMOS devices in high radiation environments are active parasitic devices which occur within the CMOS devices themselves, particularly field isolation MOS ("field transistor", or "parasitic field transistor"; used interchangeably herein) and parasitic SCR (silicon controlled rectifier) structures. These structures are well known to those skilled in the art of semiconductor processing. NMOS (the n-channel part of the complementary pairs of transistors in CMOS structures) field transistor leakage and parasitic SCR latch-up are known to cause fatal (unrecoverable) misoperation of CMOS designs in high radiation environments. NMOS field transistor leakage is known to be induced by large negative threshold shifts in parasitic field transistors as a cumulative effect of radiation. This effect, being cumulative, permanently destroys the usefulness of CMOS devices over time as a function of the total dose of radiation received by the CMOS devices. (Numerous prior-art techniques are available for dealing with parasitic SCR structures, and are beyond the scope of this specification.)
Numerous radiation tolerant (rad-hard) designs of CMOS devices have been proposed and implemented. Typically, these designs are significantly larger and/or slower than their conventional CMOS counterparts. Since the NMOS transistors in CMOS structures are particularly sensitive to radiation effects, particularly field inversion in parasitic transistors, many techniques are aimed primarily at protecting only the NMOS transistors by such methods as building guard structures or guard rings into the n-channel devices which adjust the threshold of the parasitic transistors. Examples of such techniques for creating rad-hard CMOS devices and the characterization thereof are given in H. Hatano and Satoru Takatsuka, "Total Dose Radiation-Hardened Latch-up Free CMOS Structures for Radiation-Tolerant VLSI Designs", IEEE Trans. Nucl. Sci., vol NS-33, no. 6, 1986; and in commonly-owned U.S. Pat. No. 5,220,192 (issued Jun. 15, 1993).
These "guard" techniques provide significant improvement in total-dose radiation hardness, but can often require significantly more space than is required for their non-radiation-hard counterparts, and may increase the risk of N+/P- junction breakdown.
Other techniques which may be used to improve total-dose radiation hardness include:
1) Change the size of the island mask (used to control the size of the N+ source and drain diffusion "islands") to increase the spacing to the N+ diffusion. This technique has the disadvantage of dramatically increasing the size of the transistor, reducing overall circuit density, and is only partially effective.
2) Perform a blanket P- implant to adjust parasitic field transistor thresholds. This technique reduces field leakage, but increases parasitic capacitances (reducing the speed of the transistor), does not act as an additional field guard ring (increases risk of field inversion), and increases the risk of N+/P- junction breakdown.
3) Use a nitride passivation layer. This technique reduces field leakage, but increases CMOS threshold shifts (changes active characteristics of CMOS circuits), limiting total dose radiation tolerance.
4) Photo-implant a guard structure such as that described in commonly-owned U.S. Pat. No. 5,220,192. This technique provides good overall characteristics, but increases the risk of N+/P- junction breakdown, increases the transistor size slightly, and may be difficult, if not impossible to implement when smaller sub-micron geometries are employed.
As a final processing step, a passivation layer, typically nitride or oxide (or some combination thereof), is usually applied to CMOS integrated circuitry, which is then etched to expose the bond pads areas below. This passivation layer provides a moisture barrier, acts as an ion "getter" for contaminants and, in general, protects the integrated circuit against the outside environment during the assembly process.
It has been observed that nitride passivation reduces n-channel field leakage during total-dose radiation and is an excellent moisture barrier, but has a troubling side-effect. Nitride passivation can cause CMOS threshold shifts due to a trapped charge phenomenon resulting from "interface state generation". As a result of this phenomenon, there is an increase in the resulting CMOS device's sensitivity to smaller total radiation doses. This interface state generation effect occurs as a result of the interaction of photon radiation with Si--H (silicon-hydrogen) bonds which occur as a natural result of nitride passivation. While the nitride passivation protects the n-channel transistors from field-effect leakage, this trapped charge effect reduces the radiation resistance of the p-channel and n-channel devices by causing substantial drive current and threshold shift degradation.
Oxide passivation, on the other hand, gives considerably lower CMOS threshold shifts, but does not protect the n-channel devices from radiation-induced field leakage and is not as good a moisture barrier as nitride.
"Hot" carriers, such as electrons or holes, affect CMOS devices in much the same way that radiation does, i.e., so-called "hole trapping" and interface state generation due to hot carrier impact, which causes degradation of CMOS devices in the form of mobility, drive current and threshold voltage degradation. High-energy electrons resulting from normal operation of an NMOS device strike the drain area of NMOS devices, creating trapped charge and interacting with hydrogen in the oxide to generate interface states similar to those produced by ionizing radiation. Unfortunately, since the source of hot electrons is internal to the CMOS device and is a product of normal operation of the device, the shielding methods used to provide radiation hardness are of little or no use against hot electrons. A key to reducing "hot electron" degradation is the removal of hydrogen from the gate dielectric.
"Hot Electron Resistance" is the capability of a CMOS device to withstand prolonged exposure to hot electrons. Traditional measures to improve hot-electron resistance involve structural modifications to CMOS devices to lessen susceptibility to CMOS threshold shifts. Examples of such techniques are: re-design of the CMOS drain structures making performance tradeoffs to favor hot electron resistance; operation of the CMOS device at reduced supply voltages to reduce the energy level of the electrons; of providing reduced hydrogen content through the use of plasma-CVD dielectric materials. These measures tend to degrade CMOS performance (slow), increase device size, add cost and complexity, and are generally hard to control. They are also difficult to accomplish with low-cost plastic packaging.
While neither oxide nor nitride passivation provides the combination of characteristics required for high total-dose radiation-hard CMOS circuitry, or good hot carrier resistance, the concept of using passivation to harden CMOS devices against radiation and hot carrier resistance is particularly attractive, since it requires virtually no additional circuit area, does not appreciably slow the circuitry, and is a relatively simple process.
The techniques of the prior art described hereinabove have been discussed with respect to CMOS devices, however, the problems of the prior apply equally to any semiconductor technology which incorporates MOS devices, including mixed technologies (e.g., bipolar and MOS transistors on the same semiconductor die).